Principal Verification Engineer

Description :Product validation engineer to work on key Palladium technologies including UPF. Position is based in Noida/Bangalore. Role involves verification of various upcoming features in Palladium. Work also involves managing current set of regressions. Participate in technical discussions, including Functional Specification reviews, Testplan reviews etc Review and guide team members on technical deliverables from the team Person will be fully responsible and accountable for quality of releases and features for Palladium emulation technology. Mentor juniors in the team Contribute towards the improvement of existing emulation validation/verification flows Position Requirements: The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in Emulation/UPF will be big plus. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) specially Palladium with focus towards debugging design/ verification problems. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Behavioral skills required: Must possess strong written, verbal and presentation skills. Good communication and interpersonal skills, demonstrate teamwork and collaboration skills. Ability to establish a close working relationship with both customer peers and management. Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t.