Sr. Emulation Engineer

Sr. Emulation Engineer Job Description 4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu) Working knowledge of System Verilog & Verilog language semantics and compilation flows Solid understanding on SOC architecture and AXI protocol Good communication skills and team collaboration Experience: 3 to...

Sr. Emulation Engineer Job Description 4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu) Working knowledge of System Verilog & Verilog language semantics and compilation flows Solid understanding on SOC architecture and AXI protocol Good communication skills and team collaboration Experience: 3 to...

Sr. Emulation EngineerJob Description- 4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)- Working knowledge of System Verilog & Verilog language semantics and compilation flows- Solid understanding on SOC architecture and AXI protocol- Good communication skills and team collaborationExperience: 3...

Sr. Emulation EngineerJob Description4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)Working knowledge of System Verilog & Verilog language semantics and compilation flowsSolid understanding on SOC architecture and AXI protocolGood communication skills and team collaborationExperience: 3 to 8...

Sr. Emulation EngineerJob Description4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)Working knowledge of System Verilog & Verilog language semantics and compilation flowsSolid understanding on SOC architecture and AXI protocolGood communication skills and team collaborationExperience: 3 to 8...

Sr. Emulation Engineer Job Description 4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu) Working knowledge of System Verilog & Verilog language semantics and compilation flows Solid understanding on SOC architecture and AXI protocol Good communication skills and team collaboration Experience: 3...

Sr. Emulation Engineer Job Description 4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu) Working knowledge of System Verilog & Verilog language semantics and compilation flows Solid understanding on SOC architecture and AXI protocol Good communication skills and team collaboration Experience: 3...

Sr. Emulation EngineerJob Description4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)Working knowledge of System Verilog & Verilog language semantics and compilation flowsSolid understanding on SOC architecture and AXI protocolGood communication skills and team collaborationExperience: 3 to 8...

Sr. Emulation EngineerJob Description4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)Working knowledge of System Verilog & Verilog language semantics and compilation flowsSolid understanding on SOC architecture and AXI protocolGood communication skills and team collaborationExperience: 3 to 8...

SSOC Design Verification Engineer - Senior / Lead / Sr. Experience: 5 to 12 Years Experience of working in complex test-bench/model in Verilog, System Verilog or System C. Experience of working on Functional Verification, So C Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM...