Senior Physical Verification Engineer

About Analog Devices Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and. The Senior Physical Verification Engineer is responsible for full‑chip and block‑level signoff of advanced ASIC/SoC designs, ensuring manufacturability and compliance with foundry design rules and internal quality standards. The role involves driving physical verification methodologies, debugging complex violations, and partnering closely with physical design, circuit, and CAD teams to achieve clean tape‑outs on schedule. Key responsibilities Own and execute physical verification (PV) for block and full‑chip, including DRC, LVS, ERC, ANT/antenna, ESD and density checks using industry‑standard signoff tools (e.g., Calibre, ICV, Pegasus). Debug PV violations, root‑cause issues (shorts, opens, mismatches, antenna, spacing, connectivity), and drive fixes with physical design, custom/analog, and integration teams until clean signoff. Develop, maintain, and automate PV flows and runsets for new technology nodes and design styles, improving runtime, coverage, and ease of debug. Collaborate with CAD/EDA teams to integrate PV flows into the overall implementation and signoff infrastructure, including regression, version control, and reporting. Work with foundries on PDK deployment, qualification, and updates, including rule deck validation and correlation of PV results to process changes. Provide guidelines and best practices to floorplanning, P&R, and custom layout teams to minimize late‑stage PV issues and ensure layout complies with design rules and reliability constraints. Support tape‑out preparation: manage PV signoff checklists, documentation, waivers, and risk assessment for schedule‑critical projects. Mentor junior engineers on PV methodologies, tools, and debug techniques, and contribute to technical reviews across projects. Required qualifications Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering or related field. 5–10+ years of experience in ASIC/SoC physical verification, with proven ownership of block and/or full‑chip signoff at advanced nodes (e.g., 7 nm and below, or as relevant to your environment). Strong hands‑on expertise with one or more PV signoff tools (Calibre, ICV, Pegasus, Assura, etc.), including running and debugging complex DRC/LVS/antenna checks. Solid understanding of digital physical design concepts such as floorplanning, power and clock distribution, placement/route, and integration, enabling effective collaboration with PD teams. Proficiency in scripting (Python, Perl, Tcl, or shell) for flow automation, log parsing, and custom reporting. Preferred skills Knowledge of working with Virtuoso and Skill scripting. Experience in developing or modifying DRC/LVS rule decks or runsets for major signoff tools. Exposure to custom/analog/mixed‑signal layout verification and ESD/reliability checks. Familiarity with PDK contents, technology files, and foundry interaction for advanced nodes. Strong communication skills and a track record of cross‑functional collaboration in fast‑paced design environments. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days