RTL Principal Design Engineer

1. Proficient in Verilog coding and RTL design, data path designs,2. Knowledge of RTL checks ex- LINT, SDC, CDC3. Familiar with synthesis flow and timing constraints4. Experience in writing Verilog testbench and running simulations. 5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/DisplayNature of work:The Candidate will be responsible for the...

1. Proficient in Verilog coding and RTL design, data path designs,2. Knowledge of RTL checks ex- LINT, SDC, CDC3. Familiar with synthesis flow and timing constraints4. Experience in writing Verilog testbench and running simulations. 5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/DisplayNature of work:The Candidate will be responsible for the...

1. Proficient in Verilog coding and RTL design, data path designs,2. Knowledge of RTL checks ex- LINT, SDC, CDC3. Familiar with synthesis flow and timing constraints4. Experience in writing Verilog testbench and running simulations. 5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/DisplayNature of work:The Candidate will be responsible for the...

1. Proficient in Verilog coding and RTL design, data path designs,2. Knowledge of RTL checks ex- LINT, SDC, CDC3. Familiar with synthesis flow and timing constraints4. Experience in writing Verilog testbench and running simulations. 5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/DisplayNature of work:The Candidate will be responsible for the...

1. Proficient in Verilog coding and RTL design, data path designs,2. Knowledge of RTL checks ex- LINT, SDC, CDC3. Familiar with synthesis flow and timing constraints4. Experience in writing Verilog testbench and running simulations.5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/DisplayNature of work:The Candidate will be responsible for the...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

•Exp level 5 to 8 yearsExpertise and hands on experience in Verilog/RTL design for IP or SoC.• Command and thorough knowledge on digital logic design concepts.• Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.• Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging...

•Exp level 5 to 8 years Expertise and hands on experience in Verilog/RTL design for IP or SoC. • Command and thorough knowledge on digital logic design concepts. • Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture. • Must have experience in Synopsys/Cadence/Mentor simulation tools and...

•Exp level 5 to 8 yearsExpertise and hands on experience in Verilog/RTL design for IP or SoC.• Command and thorough knowledge on digital logic design concepts.• Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.• Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging...

•Exp level 5 to 8 yearsExpertise and hands on experience in Verilog/RTL design for IP or SoC.• Command and thorough knowledge on digital logic design concepts.• Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.• Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging...

•Exp level 5 to 8 yearsExpertise and hands on experience in Verilog/RTL design for IP or SoC.• Command and thorough knowledge on digital logic design concepts.• Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.• Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

Principal Application Engineering role: This unique opportunity combines usage of industries latest and best Synopsys implementation tools, solving top notch critical design challenges, working on latest cutting-edge technology nodes and working towards enhancing QOR metrics to achieve best in class PPA and TAT targets of today's emerging semiconductor...

Level: 5 to 8 years of experience Expert in Verilog/RTL design for IP or SoC Thorough understanding of digital logic design concepts Worked on at least one large IP block with deep knowledge of IP block design/architecture Proficiency in Synopsys/Cadence/Mentor simulation tools and debugging Desirable: Knowledge of Perl/TCL scripting and...

1. Proficient in Verilog coding and RTL design, data path designs, 2. Knowledge of RTL checks ex- LINT, SDC, CDC 3. Familiar with synthesis flow and timing constraints 4. Experience in writing Verilog testbench and running simulations. 5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/Display Nature of work: The Candidate will be responsible for...

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a...