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NAND Design Rule Engineer
3 months ago
WelcomeAs a NAND Design Rule Engineer in Process Integration (Technology Development Group), your primary role is to drive and contribute to next generation Advanced NAND development efforts. You will be working with several peer groups to define, implement, and coordinate effective actions to enable multiple projects to hit key achievements and timelines.Responsible for Design rule release, Design Rule check waivers, Mask and related DRC definitions, Mask review and sign off, Process Requirement Specifications, etc. for R&D and Production DesignsDrive/Contribute to deliver key milestones starting from Project Kick Off till End of LifeCollaborate with a network of stakeholders including Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability to help direct development efforts for a new Advanced NAND generationEnsure the quality of DRCs (Design Rule Checks) released with appropriate reaction to deviation from established design rules and proper documentationWork with Yield Enhancement, Product Engineers, Defect analysis, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & DesignHelp design and evaluate test structures to provide data for next generation devices and to quantify process margin on current devicesSummarize complex problems, derive, and explain actions taken to address themDrive effective multi-functional communication on issue resolution, and support across node Design Rule alignmentDefine sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelinesEnsure the best possible communication between NAND Design Rule and other key stakeholdersEnthusiastically identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniquesAssure timely documentation and feedback of R&D activities regarding design rule improvements to production parts still in design phase.what sets you Apart5 years of experience in semiconductor industry in the areas Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process DevelopmentExposure to design & layout, ability to do minor layout and experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE is highly desiredProven capability to successfully resolve sophisticated issuesUnderstanding of Advanced NAND process flow, as well as the function and purpose of major NAND components, such as BL sensing, Word-line driver, CMOS under array, etc.Familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticleMaster's Degree or higher in Electrical Engineering, Microelectronics, Physics, or related field with 5 years of experience in semiconductor industry.
