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Design Engineer

4 weeks ago

Ahmedabad, Gujarat, India VeriFast Technologies Full time

Key Responsibilities:

  1. Design and develop RTL for ASIC/FPGA systems using Verilog and VHDL
  2. Define and implement Micro-Architecture specifications based on system-level requirements
  3. Perform RTL Integration, Synthesis, Linting, and STA (Static Timing Analysis)
  4. Execute CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and LEC (Logical Equivalence Check)
  5. Collaborate with architecture, verification, and backend teams throughout the design cycle
  6. Automate design and verification flows using scripting

Must have Experience:

Minimum 5+, ideally 7+ years of experience with any 2 or 3 of the following is must:

  1. "SoC" OR "System-on-a-Chip"
  2. "PCIe" OR "PCI-E"
  3. CPU OR processor OR RISC

Required Skills:

  1. Strong understanding of Digital Design and Micro-Architecture Development
  2. RTL coding expertise in Verilog and VHDL
  3. Basic knowledge of SystemVerilog
  4. Hands-on experience with Lint, Synthesis, LEC, CDC, RDC, STA, and RTL Integration
  5. Experience working in Linux environments
  6. Scripting skills in TCL, Python, Perl, or Shell