Analog Layout Engineer

1 month ago

india Cyient Full time

Senior Engineer -- Analog Layout

Job Location: Hyderabad (ODC Project)


Job Description


  • Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFet processes like 180nm to 3nm.
  • Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
  • Excellent understanding of CMOS / Bi-CMOS / SOI / FinFet process Excellent understanding of Analog Layout concepts (e.g. Matching, Electro-migration, Latch-up, Coupling, Crosstalk, IR-drop, Active and Passive parasitic devices etc.
  • Basic device understanding of schematic /circuit design.
  • Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
  • Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout.
  • Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.
  • Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area .
  • Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of Virtuoso -XL .
  • Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery Responsible for timely and quality execution of Custom Layout design.
  • Excellent communication skills and proactive at work.
  • Good to have: High learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment. Knowledge of Skill code layout automation.


Mandatory Skills

Mentor Graphics Calibre,Mentor Graphics Tools,Cadence Tools,Communication,Layout Versus Schematic (LVS),Design Rule Checking (DRC),Virtuoso XL

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