Staff Engineer Verification

2 weeks ago

vadodara, India Infineon Technologies Full time
This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products.In your new role you will:
This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products. Architect and develop test benches and environments. You will create, simulate, and debug test scenarios, and lead regressions and issue tracking. There will be collaboration with design and systems engineering teams to review specifications and architecture, extract features, and define verification plans. You'll drive coverage analysis and closure , and collaborate with /support digital + mixed-signal co-simulations using SystemVerilog analog behavioral models. Working closely with Analog team and AMS simulation and verification. Define verification plan and verification architecture required forverifying required RTL You are best equipped for this task if you have:
Bachelors/Master’s degree in Electronics /Electrical Engineering 3-10 years of Industry experience Digital DVLeadership experience verifying complex IP with a track record of robust ASICs.Advanced knowledge of ASIC verification flows with SystemVerilog and UVM.Experience developing test benches from scratch, bringing up designs in simulation.Skills with constrained random testing, coverage closure, and RTL /gate simulations.Proficient in a scripting language such as Python, Perl, Bash or similar. Great teammate / mentor with excellent communication skills and thedesire to seek diverse challenges. Exposure to AMS verification is a Plus and would be given preferenceUnderstanding of RTL + Spice simulationWillingness to learn basics of analog designFamilarity with VerilogA and other modeling should be ehlpeBasic Analog concepts like KCL, KVL etc.Exposure to AC2DC or DC2DC products is a great advantageWillingness to work with analog team for top level AMS verification.

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