Sr Principal DFT Engineer

1 month ago

Bengaluru, India Cadence Design Systems Full time

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary:

Join a growing and dynamic team and help lead the Design for Test activities for next generation of SoCs in advanced technology nodes. As part of the HSV SoC design team, you will be working to define and implement the Design-for-Test architecture and features for SoCs for Palladium® Emulation platforms in advanced technology nodes.

Key Responsibilities

  • Define the DFT Architecture for the next generation SoCs.
  • Implementation & verification including Scan, PMBIST, JTAG and other DFT’s related logic.
  • Define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc
  • Working closely with cross functional teams to develop and verify DFT’s structures and constraints.
  • Perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality.
  • Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.
  • Work closely with EDA RnD teams to propose and implement new features.

Requirements :

  • B. Tech /BE/ME/M Tech with 8-15+ years of relevant hands-on experience in Design for Test (DFT).
  • Clear understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
  • Working knowledge of RTL coding in Verilog, Synthesis & STA
  • Experience in at least one scripting language like PERL, Python, TCL, or Shell is preferred.
  • Hands on experience with either Tessent/Modus ATPG tool
  • Proven success in development of complex custom ASIC products in advanced process nodes
  • Hands-on experienced and successful taped out several ASICs.
  • Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
  • Excellent written and verbal communication skills.

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