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Design Verification Engineer
1 month ago
Are you a seasoned professional with over 3 years of experience in ASIC/FPGA verification? We're looking for a dynamic and skilled individual to join our team
Key Qualifications:
Proven expertise in System Verilog and a MUST-have proficiency in UVM.Extensive hands-on experience in IP/Sub-system/SOC Verification.Track record in coverage-driven verification methodologies.Strong proficiency in creating and maintaining testbenches (stimulus, agent, monitor, checker).Proficient in failure debugging using industry-standard tools such as Verdi, DVE, Simvision, and log file analysis.Solid background in SOC verification with C/ASM-based test development.Expertise in assertion development.Familiarity with EDA tools like IUS, VCS, Questasim, etc.Proficiency in scripting languages such as Perl and Python.A collaborative team player with excellent communication skills, capable of proactive interaction with designers and fellow verification engineers.
Additional Experience:
Exposure to various verification tasks, including gate-level simulation, power-aware simulation, formal verification, sub-system verification, and emulation.Knowledge of AMBA protocols, High-Speed and Low-Speed peripherals, Memory interface protocols, image processing, etc.If you're passionate about pushing the boundaries of verification in a collaborative environment, this is the perfect opportunity for you Join us in creating cutting-edge solutions and contribute to the success of our innovative projects.
Apply now and be part of a team that values expertise, innovation, and a commitment to excellence
#VerificationEngineer #ASIC #FPGA #SystemVerilog #UVM #EDA #Python #Perl #InnovationInTech #SoC
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