DFT - Timing

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER Locaton: Bangalore THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Define, develop, and maintain precise DFT-specific timing constraints (scan shift/capture, MBIST, LBIST) ensuring full timing closure without impacting functional timing. Perform static timing analysis (STA) sign-off on DFT structures (scan chains, BIST controllers, test logic), analyze timing reports, and debug violations. Validate timing integrity of test clocks, scan enable signals, and control signals across multiple test modes and PVT corners. Collaborate with design, physical design, and timing teams to resolve test logic timing issues while maintaining overall chip performance. Ensure DFT timing constraints correctly handle false and multi-cycle paths to avoid timing misinterpretations. Develop and maintain automation scripts (TCL, Python, Perl) to streamline STA and DV flows, improve efficiency, and generate detailed reports. Develop and execute comprehensive design verification (DV) plans focused on scan chain insertion, test logic functionality, and robustness. Create and run verification testbenches for scan chain operations (shift, capture, reset, bypass) and validate DFT features (scan, BIST, compression) via simulation/emulation. Collaborate with ATPG teams to validate test pattern quality and fault coverage, ensuring high-quality manufacturing test readiness. Measure and improve test coverage metrics; identify and debug scan-related failures during pre-silicon simulation and support post-silicon debug activities. Actively contribute to improving DFT timing methodologies and DV verification environments based on silicon feedback and industry best practices. Work cross-functionally with design, validation, and physical teams to address DV issues and provide feedback to enhance design testability. Document and report DV plans, timing closure status, verification results, and issues to facilitate clear communication across teams. Mentor junior engineers on best practices in DFT timing closure and design verification. PREFERRED EXPERIENCE: Strong hands-on experience in developing and managing timing constraints for scan chains, BIST, and test logic, with expertise in static timing analysis (STA) sign-off using tools like Synopsys PrimeTime or Cadence Tempus. Proven ability to debug and resolve timing violations related to DFT logic, collaborating effectively with design and physical teams to achieve timing closure. Solid background in creating and executing design verification plans for scan chain functionality, BIST, ATPG validation, and compression logic using simulation and verification methodologies. Proficiency in scripting languages (TCL, Python, Perl) for automation of STA and DV flows, test coverage analysis, and regression management. Experience with industry-standard DFT and verification tools such as Synopsys DFT Compiler, Mentor Tessent, and TetraMAX. Familiarity with test pattern generation and validation, ensuring high fault coverage and minimal test patterns. Exposure to multi-mode, multi-corner STA methodologies and test mode timing verification (scan, LBIST, MBIST). Ability to collaborate cross-functionally and contribute to post-silicon debug and silicon bring-up support. Knowledge of advanced node SoC design flows and best practices in DFT timing and DV methodologies ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.SENIOR SILICON DESIGN ENGINEER Locaton: Bangalore THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Define, develop, and maintain precise DFT-specific timing constraints (scan shift/capture, MBIST, LBIST) ensuring full timing closure without impacting functional timing. Perform static timing analysis (STA) sign-off on DFT structures (scan chains, BIST controllers, test logic), analyze timing reports, and debug violations. Validate timing integrity of test clocks, scan enable signals, and control signals across multiple test modes and PVT corners. Collaborate with design, physical design, and timing teams to resolve test logic timing issues while maintaining overall chip performance. Ensure DFT timing constraints correctly handle false and multi-cycle paths to avoid timing misinterpretations. Develop and maintain automation scripts (TCL, Python, Perl) to streamline STA and DV flows, improve efficiency, and generate detailed reports. Develop and execute comprehensive design verification (DV) plans focused on scan chain insertion, test logic functionality, and robustness. Create and run verification testbenches for scan chain operations (shift, capture, reset, bypass) and validate DFT features (scan, BIST, compression) via simulation/emulation. Collaborate with ATPG teams to validate test pattern quality and fault coverage, ensuring high-quality manufacturing test readiness. Measure and improve test coverage metrics; identify and debug scan-related failures during pre-silicon simulation and support post-silicon debug activities. Actively contribute to improving DFT timing methodologies and DV verification environments based on silicon feedback and industry best practices. Work cross-functionally with design, validation, and physical teams to address DV issues and provide feedback to enhance design testability. Document and report DV plans, timing closure status, verification results, and issues to facilitate clear communication across teams. Mentor junior engineers on best practices in DFT timing closure and design verification. PREFERRED EXPERIENCE: Strong hands-on experience in developing and managing timing constraints for scan chains, BIST, and test logic, with expertise in static timing analysis (STA) sign-off using tools like Synopsys PrimeTime or Cadence Tempus. Proven ability to debug and resolve timing violations related to DFT logic, collaborating effectively with design and physical teams to achieve timing closure. Solid background in creating and executing design verification plans for scan chain functionality, BIST, ATPG validation, and compression logic using simulation and verification methodologies. Proficiency in scripting languages (TCL, Python, Perl) for automation of STA and DV flows, test coverage analysis, and regression management. Experience with industry-standard DFT and verification tools such as Synopsys DFT Compiler, Mentor Tessent, and TetraMAX. Familiarity with test pattern generation and validation, ensuring high fault coverage and minimal test patterns. Exposure to multi-mode, multi-corner STA methodologies and test mode timing verification (scan, LBIST, MBIST). Ability to collaborate cross-functionally and contribute to post-silicon debug and silicon bring-up support. Knowledge of advanced node SoC design flows and best practices in DFT timing and DV methodologies ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AA1Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.