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Senior/Staff Verification Solutions Engineer
1 month ago
Key Requirements
- Experience: Bachelor’s degree in Electronics with 7-10+ Years’ or Master’s degree in Electronics with 5-8+ Years'- Experience in verification technologies (Simulation, UVM, SVA, LRM understanding)- Strong HDL language support (Verilog, VHDL, System Verilog)- Simulation, UVM, Design Verification- Digital design fundamental and RTL coding understanding- Good Debugging skills.- Scripting – Perl, TCL, Make, Shell Scripting.- Role - VCS Simulation Technology Product Engineer- Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog- Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, Verdi) would be added advantage.- Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions.- Must have working knowledge on UNIX, TCL and/or any other scripting language to be effective.- Team player, partners with multiple stakeholders, has attention to detail and innovative mindset.- Motivated, doer and self-organized team worker with good social communication skills- Open to travel, ability to multi-task, be detail-oriented.- Drive VCS/related technology customer deployment working closely with field and R&D- Drive competitive engagements, requirements gathering for delivery strong product roadmap.- Work directly with R&D, Product Validation & Customers to suggest improvements in implementation and validation.- Use in-depth product understanding to provide technical expertise, diagnose, troubleshoot issues.
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