Senior Manager Memory Circuit Design Verification

3 weeks ago


hyderabad, India Spectrum Consultants India Private Limited Full time
Senior Manager Memory Circuit Design Verification Summary
Experience Required:
13 - 20 Years
Job Term:
Permanent
Location:
Hyderabad
Category:
Semiconductor Design
World leader in innovative memory solutions
Description
As a Senior Manager Memory Circuit Design Verification Engineer / Principal Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally correct design.
Unique Opportunities
· Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s.
· Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.
· Work on cross functional tasks that can widen your skill set.
Responsibilities
· Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
· Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
· Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
· Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
· Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
· Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
Core Requirements
· Good communication skills and ability to work well in a team
· Guide new team members and young engineers in the team
· Analytical capability for complex CMOS and/or gate level circuit designs
· Well versed with either SPICE and/or Verilog simulations
Preferred Qualities
· Experience in SystemVerilog, PLI coding
· Experience in UVM Test Bench
· Experience in DRAM, SRAM or other memory related fields
· Experience in AMS verification and co-sim
Education
Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required.


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