Staff Engineer – ASIC Digital Design(DDR PHY)
2 weeks ago
JOB Description:To be part of a highly skilled and challenging high speed parallel PHY such as DDR, LPDDR etc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of design and verification from spec to silicon along with interface design for controller and SoC.Active involvement in problem solving and implementing opportunities for improvementMentoring and coaching other design team members on technical issuesPair with Analog designers to ensure smooth interface between Digital and Analog circuitsEqual opportunity position with excellent pay package
SKILLS required:
Strong fundamental knowledge of digital design, Verilog and scripting languagesExperience with micro-architecture and Asynchronous digital designsWorking knowledge of Synthesis, STA, Lint & CDCWorking knowledge of DDR/LPDDR JEDEC protocol and DDR PHY designsExperience with DDR training algorithms and data path designsExperience in domain transfer designs, APB/JTAG, DFI, BS/BE (Electronics)Experience Required
: 7+ Years
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