DFT Director
2 days ago
Location: Bangalore
Location: Bangalore
The selected candidate will be a key contributor who is responsible for DFT logic design, implementation, verification and vector generation..
Responsibilities
Implementing DFT architecture features in the design.
SCAN insertion, scan DRC analysis and debug.
Achieving high SCAN coverage and low DPPM.
ATPG vector generation and ATE BringUp.
JTAG implementation and verification.
MBIST / LBIST and JTAG implementation and verification.
IP-SOC integration methodology and Implementation of DFT structures to support IP test requirements.
Contributions to overall DFT flow / automation.
Contributions to SCAN, MBIST and JTAG timing constraints/analysis.
Simulation and Verification of DFT structures in the design
Requirements
BTech/MTech preferred.18+ years experience
Strong understanding of DFT methodologies and experience in standard DFT tools.
Experience on SoCs with multiple scan chains and clocks.
Hands On experience in SCAN/MBIST/LBIST/JTAG implementation at chip & block level.
Knowledge on DFT simulations and debugging.
Knowledge on Test mode timing constraint development and analysis is a plus.
Understanding of test compression and ATE debug is a plus.
Having strong scripting abilities is a plus.
experience in Systemverilog, Verilog,Tessent/DFT Max /TestMax /Tetramax /Modus
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
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