VLSI Design Verification Engineer

2 days ago

india Aiml Services Pvt Ltd Full time

Company Description


AIML is one of the premier Defence & Semicon company founded in September 2018 by young entrepreneur industry veterans with vast experience in Defence & Semicon experience i.e., Design Verification, physical design, analog layout, physical verification, etc.


Recently we have achieved a significant milestone with the development of two groundbreaking products exclusively for Indian Defence sector. This accomplishment represents a major leap forward in indigenous innovation and technological capability. These advancements not only strengthen national security but also demonstrate India's strides towards self-reliance and leadership in the defense industry.


AIML has a highly experienced team that can handle all stages from RTL/Netlist to GDS II and has successfully taped out many IPs, sub-systems, and chips.


With a senior physical implementation team and physical architects specialized in diverse domains, we are well-positioned to own and execute projects in ownership mode. The AIML Services team has experience in all the major industry-standard EDA tools.


Role Description

This is a full-time role for a Design Verification Engineer with 5+ years of experience. The DV Engineer will be responsible for the day-to-day tasks associated with digital verification, including test plan development, testbench creation, test case development, simulation, and debugging. The role is located in Bengaluru and offers flexibility for remote work.


Responsibility

  • To be part of a highly skilled ASIC Team working on the newest technology nodes
  • Responsible for overall IP verification from test plan creation, UVM development to signoff.
  • Pair with similar domain specialists across other geographical locations on core technical initiatives
  • Strong experience in digital verification and familiarity with industry-standard methodologies
  • Proficiency in System Verilog TB, UVM Methodology, Debug and VIP Development
  • Exposure of SERDES/UNIPRO/PCIE/UFS/DDR protocols is an advantage
  • Exposure to verification of complex high speed PHY
  • Experience with testbench development, test case creation, simulation, and debugging
  • Proven track record of building testplan, UVM environment and testbenches
  • Experience with RTL debugging, ScoreBoarding and Code Coverage Analysis

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