STA Synthesis Engineers

Position: STA Location: Bangalore, India Duration: Full Time Job Description: Design constraints creation using architecture/micro arch specs. Good understanding of various external IO protocols (I2C, SPI, UART etc) Design constraints validation across multiple corners/modes using TCM (Synopsys) / Timevision (Ausdia) Run Primetime and validate...

Title: PD(Synthesis) Engineer Description Full chip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Full chip timing - Primetime constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. Voltage Island - Coarse level UPF/ Clock gating.

Company: Eteros Technologies India Private LimitedEteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad• Our world-wide customers are amongst The Who's...

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The...

Job Description Job title: Lead STA Engineer Experience: 7-10 years Primary Responsibilities: The STA and Methodology Engineer is expected to work closely with the Foundation IP teams (Standard cell, IO, and Memories teams) and NXP NPI design teams spread across various BL's to support timing and Power analysis and closure while making sure a seamless use...

Work with top/block level Synthesis, Timing closure (STA). DCT/DCG based Synthesis, Equivalence checks. Well versed with tcl / Perl script Will work on UPF and Conformal Low Power checks Work with top/block level Synthesis, Timing closure (STA). DCT/DCG based Synthesis, Equivalence checks. Well versed with tcl / Perl script Will work on UPF and Conformal Low...

Experience: 4+ years Skills Required: STA timing check. Eco prepare VCLP LDRC Formality

Principal Engineer STA (10-15) years experience) Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design. Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals? Are you interested in developing novel and exclusive technology...

Senior Principal Engineer/ Principal Engineer, STA (10-20 years experience) Location: Bangalore Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design. Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals? Are you...

Hi All, We are looking for PD(Front-end Synthesis ) Engineers/Leads. Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Fullchip timing - PrimeTime constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. Voltage Island - Coarse level UPF/ Clock...

Design For Test(DFT) DFT Skill set required with below split of 10 DFT CW - preferably with 5-7 yrs of exp. * 2 CW : Experience with MBIST/Mint flows and methodology * 3 CW : Experience with SSN architecture/implementation/validation * 4 CW : Experience with Taplinks/STF/BSCAN implementation/validation * 1 CW : Experience with Intel...

Location: Bangalore/Hyderabad Experience: 5-12yrs Notice Period: Immediate to 15 Days Primary Skills : Physical Design, CTS, STA & Physical Verification · Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. · Should have experience on Physical Design...

Job Description Open Position: Senior Design Automation Engineer (MNC Semiconductor Company) A MNC Semiconductor company is looking for Senior Design Automation Engineer to join the team and be based in the Penang R&D Center. You will be involved in the RTL synthesis to layout design (GDSII), supporting DFT insertion, ECO logic flows, LEC flow, Front-End...

We are looking for Multiple roles to fullfill San Diego, CA and Austin, TX (two different positions) To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM. Work On PD projects. Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing...

Quest Global is an organization at the forefront of innovation and one of the world’s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility. We are...

4 to 10 years relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction,...

Hi Folks Greetings from Tech Mahindra Role: Senior Physical Design Engineer Exp: 5+ years Location: Bangalore/ Ahemdabad/ Kochi/ Vizag About Job >> RTL to GDS including, Synthesis + PNR • Fusion compiler / Cadence flow (Innovus) • Good understanding Macro placement, Floorplanning, placement CTS, Routing • Design planning ( partitioning, bump...

hello Connections!!!!!!!! Immediate hiring!!! Tessolve Semiconductors is hiring for below positions Position: Sr.RTL ASIC Design Engineer Experience:4+ years Location - Bangalore Notice period: immediate to 30 days most preferable. Required Skills: B.E/B.tech in Electronics or related field with 4 to 7 years of experience. Proven hands-on experience with IP...

Senior Digital VLSI Design / Digital Design Engineer Location: Bangalore Who We Are We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in Bangalore, India and , Taiwan. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for...

Senior Principal Engineer/ Principal Engineer, Physical Design (10-20 years experience) Location: Bangalore Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design. Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals? Are...