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Staff engineer
3 days ago
Staff engineer , ASIC Design Verification
Job Description
To be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodesResponsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.Leading, mentoring and coaching junior team membersWork closely with Digital and Analog designers
Skills Required
Good experience of logic simulation, UVM environment and testbench creationExperience with timing simulation and debugExperience with RTL debugging, score boarding and code coverage analysisWorking knowledge of CDC and LintExposure to verification of complex high speed PHY and/or complex AMS IPsUnderstanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocolsSound knowledge of Verilog and System Verilog languagesExposure to modelling and validating complex analog circuits in Verilog and Verilog-AM.S./M.Tech, BS/BE (Electronics)
Experience Required: 7+ Years
Contact:UdayMulya
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