Principal Physical Design Engineer

About Analog Devices Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and. Job Description: Principal Digital Physical Design Engineer Role Overview A Principal Digital Physical Design Engineer will own and execute the physical implementation of advanced digital ICs from netlist to GDSII, ensuring optimal power, performance, and area while maintaining robust sign-off quality. The emphasis is on hands-on technical expertise and direct execution of complex implementation tasks over management responsibilities. Key Responsibilities Lead and perform all major steps of the digital physical design flow, including block-level and top-level floorplanning, placement, clock tree synthesis, routing, and timing closure. Collaborate directly with RTL and synthesis teams for timing constraint setup, synthesis refinement, and netlist quality. Develop and implement strategies for power integrity, IR-drop analysis, EM verification and low-power physical design using UPF/CPF methodologies. Hands-on execution of physical verification: DRC, LVS, ERC, antenna checks, reliability and manufacturability checks, and ECO implementations. Drive timing analysis and closure at all implementation stages, using static timing analysis (STA) and advanced node-specific signoff flows. Own integration of hard macros, blocks, and IP; define and optimize power grid, pad ring, and custom routing as required. Propose and develop automation for various physical design flows using TCL, Python, or other scripting languages for process improvement. Perform design partitioning, floorplan, and chip assembly for hierarchical and complex designs targeting advanced process nodes (≤ 7nm). Interface with DFT, signal/power integrity, package, and test teams to ensure comprehensive signoff and manufacturability. Actively contribute to methodology improvements, flow development, and CAD tool evaluations. Participate in engineering and peer reviews, providing direct, hands-on technical guidance to the team. Required Qualifications Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering or a related discipline. 10+ years’ hands-on experience in all aspects of digital physical design for ASIC/SoC development; experience with advanced FinFET nodes is a plus. Expert knowledge of EDA tools for physical design: Cadence Innovus, Synopsys ICC2, Mentor Olympus, STA tools. Deep technical expertise in timing closure, PPA optimization, physical verification, and IR-drop/EM checks. Scripting skills in TCL, Python, or Perl for workflow automation and data analysis. Proven track record of successful tapeouts (block and full chip) at advanced nodes, including hierarchical and top-level physical implementation. Experience with low-power design techniques and physical implementation of complex multi-power/voltage domain chips. Strong debug and analytical skills, including post-route timing, layout closure, and design ECO execution. Excellent ability to document flows and report findings. Nice-to-Have Skills Hands-on experience integrating mixed-signal or analog blocks, custom IPs and hard macros. Familiarity with DFT insertion, boundary scan, scan chain stitching at physical level. Involvement in physical design methodology development and CAD flow automation. Publications or patents in physical implementation, EDA flow innovations, or advanced process optimizations. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days