ASIC Design Engr 2
2 weeks ago
Infinera is one of the world's leading providers of carrier-class optical networking products and services worldwide. Our solutions carry data over subsea optical cables, between cities and data centres. Infinera is building the next generation of pluggable optical modules and compact open modular optical systems.
Infinera India Pvt. Ltd, Bangalore, is the largest Engineering group within Infinera with a team of 400+ people and is a critical execution team since the past 15 years.
Infinera India ASIC team provides ASIC and FPGA solutions for all client facing interfaces in Infinera's systems. A dedicated team of 70 ASIC engineers gets to own and work on the Architecture, Design, Verification of Next Generation client interface solutions.
As a company, Infinera has a culture and history of challenging conventional engineering thinking.
The ASIC team takes pride in its engineering acumen, its teamwork, and the difference it makes to the quality and timeliness of our ASIC solutions.
We are looking to add passionate, highly motivated, and talented Engineers to our mix of seasoned Engineers and fresh college graduates.
What we offer:
Opportunities to create solutions to challenging technical problems in area of ASICs
A view of system level thinking and processes – you get to see the bigger picture, while developing your niche
A space for continuous learning through open communication and white-board discussions
Opportunity to master IEEE and ITU standards
A technically stimulating environment while providing a good work life balance
Work as part of a team comprising of end-to-end expertise, architects, protocol experts, implementation experts in design and verification, emulation, platform experts who develop SW and FW
In this role, you will work as a part of a team in the verification of a large and complex block. In addition, you are expected to write tests, debug the failures, run regressions, work with design team, work with other verification team members.
What you will be doing:
Experience of 4+ years in Verification
Understand the system level use case
Participate in the verification planning at all stages
Testbench architecture and building or coding various part of the verification infrastructure which include test bench components, VIPs, drivers, checkers, and assertions
Document and review the test plans, implement, and execute them
Opportunities to do lab validation of the ASICs using Python
Contributions at a group level:
Support collecting various reusable verification components
Support streamlining verification flows and processes
Explore and adopt new verification methodologies
Area of work:
- UVM/System Verilog + Formal verification + Emulation + Lab Validation
- SV UVM Experience
Independently developed a testbench from scratch
Experience of complete verification cycle in at least one project
Scripting experience
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