PLL Analog Design Engineer

5 days ago

Bengaluru, India Qualcomm Full time

General Summary:

Posting Title: Analog/Mixed Signal PLL Analog Designers Bangalore (BDC), India

Job Function

Qualcomm Mixed-Signal IP team is actively seeking for analog circuit designers (3-10yrs) to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO IP for SoC and the integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products in leading-nodes - finfets & beyond. Design goals include low-power & low voltage analog designs to address Qualcomm's low-power wireless products.

Responsibilities

Hands-on experience - Analog circuit design

  • Architecture, design, and development of analog / mixed signal hard macros for the PLL IP Design team

  • Experience in designing multiple analog building blocks Bias, References, Op-amp, LDOs, VCO/DCO etc & High-Speed custom digital like dividers, distribution etc.

  • Perform custom circuit design in the latest FinFET CMOS processes technologies and deliver hard macros and support customer integration and testing.

  • Able to setup, run & analyses circuit simulations(spice) & create behaviour models.

  • Work closely with Layout, Digital designer, PD & HSIO Bench/ATE Team

  • Participate in internal customer requirements discussions to create design specifications.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Skills & Experience

  • A minimum of 2-years of transistor level analog mixed-signal design experience, preferably in PLL design, high-speed wireline SerDes, DDR or other high-speed applications
  • Experience in using SPICE simulators, adexl & virtuoso.
  • Familiar with custom analog layout parasitic LLEs optimization, post layout extraction, Verification & design review closure
  • Understanding of signal integrity in high-speed wireline design is preferred.

  • Scripting to automate circuit design and verification work.

  • Able to work with teams across the globeand possess good communication and presentationskills.

Preferred

Mixed signal designexperience

Keywords

Analog circuit Design, PLL, VCO, DCO, Clock distribution

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