Insemi Technology

Role : Standard Cell Layout.

Location : Bangalore.

Experience : 3+ years.

Role Description :

- This is a full-time on-site role in Bengaluru for a Standard Cell Layout position.

- The role involves daily tasks related to designing and implementing standard cell layouts, optimizing chip performance, and collaborating with cross-functional teams.

Qualifications :

- Proficiency in VLSI design and layout tools such as Cadence Virtuoso.

- Knowledge of CMOS processes and standard cell library development.

- Experience in physical design implementation and DRC/LVS verification.

- Strong understanding of timing analysis and power optimization techniques.

- Excellent communication skills and the ability to work effectively in a team.

Job Description :

- We are seeking a skilled Standard Cell Layout Engineer with 3-6 years of experience to join our team.

- The ideal candidate will have a strong foundation in VLSI design and layout, with expertise in standard cell library development and physical verification.

Responsibilities :

- Design and develop standard cell layouts according to given specifications.

- Perform layout verification, including DRC, LVS, and other relevant checks.

- Optimize cell layout for area, power, and performance.

- Collaborate with circuit designers to ensure layout accuracy and functionality.

- Participate in library characterization and timing analysis.

- Contribute to the development of standard cell library methodologies and flows.

Required Skills :

- Proficiency in VLSI design and layout tools, especially Cadence Virtuoso.

- In-depth knowledge of CMOS processes and standard cell library development.

- Experience in physical design implementation, including DRC and LVS verification.

- Strong understanding of timing analysis and power optimization techniques.

- Excellent attention to detail and problem-solving abilities.

- Strong communication and teamwork skills.

Preferred Skills :

- Experience with layout automation tools and scripting.

- Knowledge of layout parasitic extraction and circuit simulation.

- Experience with advanced layout techniques (e.g., optical proximity correction, layout for manufacturing).