Senior DV Engineer
1 day ago
LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design teamQualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 5 + of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 5+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVN
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DV DFT Engineer
4 days ago
New Delhi, India Proxelera Full timeWe’re Hiring: DV / DFT Engineer – Hyderabad (On-site Preferred)We are looking for a talented DV/DFT Engineer with 3–5 years of strong hands-on client project experience to join our team in Hyderabad.Key Responsibilities:• MBIST DV and MBIST insertion• SMS insertion and SMS DV• BIST insertion and BIST DV• SoC DV and SoC-level simulations• ATE...
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Senior Design Verification Engineer
2 weeks ago
New Delhi, India Nurotech circuits private limited Full timeTips: UVM, Design Verification.Responsibilities- Senior DV engineer to develop UVM/SV-based testbench - Good knowledge of SV/UVM is a must. - Should have developed UVM/SV components like driver/monitor/scoreboard, - Individual contributor role - Exposure to protocols like AMBA, Serial protocols, PCIe, EthernetQualifications- 6 to 8 years of DV experience...
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Senior Design Verification Lead
3 weeks ago
New Delhi, India HCLTech Full timeHello VLSI folks!HCL Engineering - Semiconductor - Hiring Design Verification Engineer (Senior Level - 5 to 20Years years’ experience) - Chennai, Bangalore.Interested aspirants could email your profile to magenderan.r@hcltech.com /Call 8050996119.We will discuss in details on the job profile & responsibilities.Company: HCL TechJob Summary:We are seeking a...
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Senior Design Verification Lead
2 weeks ago
New Delhi, India HCLTech Full timeHello VLSI folks!HCL Engineering - Semiconductor - Hiring Design Verification Engineer (Senior Level - 5 to 20Years years’ experience) - Chennai, Bangalore.Interested aspirants could email your profile to magenderan.r@hcltech.com /Call 8050996119.We will discuss in details on the job profile & responsibilities.Company:HCL Tech Job Summary: We are seeking a...
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Senior Design Verification Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeACL Digital Hiring for the below requirementDesignation: DV engineers Experience: 8-10+ years Location: BangaloreJob Description:1. Hands-on experiences on SV/UVM/Specman 2. Familiarity with formal-based verification 3. Running regression and debugging failures independently 4. Experience in functional and code coverages 5. Independently handling...
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Design Verification Engineer
2 weeks ago
New Delhi, India ACL Digital Full time#ACL Digital is Hiring: GPM Subsystem Verification EngineerMust-have: UVM, System Verilog, IP VerificationPreferred: Power Management IP, Firmware DV, Python/PerlFull-cycle DV: test plan → tape outCollaborate with top DV, design & architecture teamsApply/Refer: himabindu.jeevarathnam@acldigital.com#ACLDigital #HiringNow #DesignVerification #UVM...
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Design Verification Engineer
2 weeks ago
New Delhi, India ACL Digital Full time#ACL Digital is Hiring: GPM Subsystem Verification EngineerMust-have: UVM, System Verilog, IP Verification Preferred: Power Management IP, Firmware DV, Python/Perl Full-cycle DV: test plan → tape out Collaborate with top DV, design & architecture teamsApply/Refer:...
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Design Verification Engineer
2 days ago
New Delhi, India Canvendor Full time#Urgent_Opening_for_Canvendor#Hiring: DV Engineer (4-10 Years Experience) |Bangalore| Immediate Joiners PreferredLocation: Chennai, IndiaExperience: 4-10 YearsNotice period: Immediate to 30daysMandatory: IP/SS verification of complex blocks (CPU SS), Fabric/NOC/Interconnect blocks, AMBA, SV, UVM#Key_Requirements:IP Verification-Experience in executing IP/SS...
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Senior Design Verification Engineer
8 hours ago
New Delhi, India ACL Digital Full timeSolid experience in SystemVerilog / UVMPCIe protocol verification expertiseStrong understanding of IP-level protocolsHands-on with DV environments, debugging & coverageAbility to work across design, architecture & validation teams#ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PCIe #VLSICareers #HyderabadJobs #BangaloreJobs
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Emulation lead engineer
4 days ago
New Delhi, India Qualcomm Full timeEngineering Group, Engineering Group > Hardware EngineeringGeneral Summary: 5+ Years of experience in Emulation Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve...
