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Design Verification Engineer

1 month ago

Bengaluru, Karnataka, India ACL Digital Full time

Job Description:

Looking for an experienced Design Verification Engineer to develop and execute verification plans for digital designs (ASIC/FPGA/SoC). Responsible for writing testbenches, creating test cases using SystemVerilog/UVM, running simulations, and debugging design issues. Collaborate with design teams to ensure design quality and coverage goals.

Requirements:

  • 4-20 years in design verification of digital ICs
  • Strong SystemVerilog and UVM knowledge
  • Experience with simulation tools (VCS, Xcelium, QuestaSim)
  • Skilled in writing assertions, coverage, and debugging
  • Familiarity with scripting (Python/TCL/Perl) and version control
  • Good understanding of digital design and RTL
  • Strong communication and teamwork skills