Principal Engineer, Design Enablement Lead

1 month ago

hyderabad, India Spectrum Consultants India Private Limited Full time
Principal Engineer, Design Enablement Lead Summary
Experience Required:
7 - 15 Years
Job Term:
Permanent
Location:
Hyderabad
Category:
Semiconductor Design
World leader in innovative memory solutions
Responsibilities include but are not limited to the following:
Coordinate the work of engineers from multiple groups and across several geographies to develop Design Rules, Requirements, Test Structures and improve process margin for all DRAM generations from early development until manufacturing ceases
Manage effort to build and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices
Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and time-lines
Pro-actively identify and address process issues and process window vs. die size issues stemming from specific database layout or layout techniques
Partner with Design, Product Engineering, Process integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM products
Assure that the right DRC’s (Design Rule Checks) are in place, assure appropriate reaction to deviation from established design rules
Strategically partner with multiple teams and fields to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design
Summarize sophisticated problems, derive and explain actions taken to address them
Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment
Maintain and implement meaningful communication between Process Integration, Product Engineering, Design, and Advanced Mask teams
Improve timely documentation of the R&D activities with regard to design rule improvements for transfer to parts still in design
Minimum Qualifications:
BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field
Senior level (5+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development
Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired
Experience with Test Structure Design and characterization
Success in resolving sophisticated issues
Think and communicate clearly in urgent and stressful situations
Possess a deep understanding of the DRAM process flow, as well as the function and purpose of major DRAM components, such as Sense Amp, Word-line driver, and Anti-Fuse
Exposure and familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle

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