Senior Design Verification Engineer
4 weeks ago
Job Summary
Cadence is seeking an experienced design verification engineer who will play a critical role in the development of custom accelerator SoCs, in partnership with Cadence computational simulation teams.
Role: Principal Design Engineer/Lead Design Engineer ( SoC team)
Job Responsibilities: (Design Verification Engineer)
- The qualified candidate will closely work together with ARCH, RTL and FW/SW team in implementation and optimization of our accelerator solution.- The candidate must possess hands-on experience and excellent debugging skills in developing System Verilog/UVM based testbenches.- Ability to independently verify complex modules in the context of subsystem/SOC using systemic metric-driven approach must be demonstrated.- Past participation in successful IP delivery or SOC tape-out is highly desired.- Effective cross-team communication and documentation skill is strongly preferred.- Experience in automating verification regression and/or management of revision control is a plus.
Qualifications
- Minimal qualification requires BS/MS degree ECE or CS with 4 -10 years of experience in Design verification.
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