Sr. Design Verification Engineer

5 days ago

Pune, India VeriFast Technologies Full time

Senior Design Verification Engineer


Location: Pune, India


We are seeking an experienced Senior Design Verification Engineer to join our team, focusing on advanced chip-to-chip interconnect verification and complex digital designs.


Key Responsibilities:

  • Lead verification planning and execution for complex digital designs with a focus on high-speed interfaces, particularly UCIe
  • Develop and maintain comprehensive verification environments using SystemVerilog and UVM
  • Create detailed verification plans, including coverage metrics and verification strategy
  • Debug complex hardware issues and drive them to resolution
  • Mentor junior verification engineers and collaborate with design teams
  • Review verification code and provide technical guidance to team members

Required Qualifications:

  • Bachelor's or Master's degree in Electrical/Computer Engineering or related field
  • 7+ years of hands-on experience in digital design verification
  • Proven experience with UCIe (Universal Chiplet Interconnect Express) verification
  • Expert-level knowledge of SystemVerilog and UVM methodology
  • Strong understanding of other standard interfaces including:
  • PCIe (PCI Express)
  • CXL (Compute Express Link)
  • DDR/LPDDR
  • AXI/AHB/APB
  • Ethernet

Technical Skills:

  • Advanced SystemVerilog and UVM concepts including virtual sequences, register modeling, and coverage-driven verification
  • Experience with assertion-based verification and formal verification methods
  • Proficiency in developing reusable verification components
  • Expertise in coverage analysis and closure
  • Familiarity with industry-standard verification tools (Synopsys VCS, Cadence IES, or similar)
  • Experience with performance analysis and debugging of high-speed interfaces
  • Knowledge of Python or Perl for verification automation

Preferred Qualifications:

  • Experience with emulation platforms
  • Knowledge of power-aware verification
  • Understanding of mixed-signal verification concepts
  • Experience with QVIP/VIP integration
  • Familiarity with continuous integration/continuous deployment (CI/CD) for verification

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