Senior design verification engineers

Eximietas Hiring Senior Design Verification Engineers/Leads (PCIE) Experience - 10+ Yrs. Location - Bengaluru or Visakhapatnam Job Description: Lead So C Design Verification efforts for complex projects, ensuring successful execution of verification plans. Develop and implement comprehensive verification strategies , including test plans,...

Eximietas Hiring Senior Design Verification Engineers/Leads (PCIE)Experience - 10+ Yrs.Location - Bengaluru or VisakhapatnamJob Description:Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans.Develop and implement comprehensive verification strategies, including test plans, testbenches, and coverage...

Job Title: Senior Design Verification Engineer Location: Bengaluru, India Experience: 5+ Years Notice Period: Less than 30 Days Job Description: We are seeking a Senior Design Verification Engineer with 5+ years of experience in So C/IP level verification . The candidate must have strong expertise in System Verilog, UVM methodology , testbench...

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/So C designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/System Verilog to create testbenches, write test...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe, NVMe, NAND,...

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write...

Senior Design Verification Engineer:Should have PCIE IP level verification exposureGood UVM understandingSerial protocol understandingInterested,please drop your updated CV to janagaradha.n@acldigital.com

Position Overview: We are seeking a highly skilled Senior Engineer/Architect to join our dynamic team. In this pivotal role, you will lead the design and verification of advanced integrated circuits (ICs), ensuring they meet the highest standards of quality and performance. This position offers the opportunity to work on groundbreaking projects and influence...