Principal Sta Engineer

5 days ago


Bangalore City, India Mulya Technologies Full time

Principal STA Engineer Top10 Semiconductor Organization in the World Bangalore We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Do you want to join inclusive Team Skills Required 10-20 years of proven experience in Synthesis/STA Good understanding of overall design Flow RTL to GDS. Experience in signing off the full chip synthesis/STA for tape-outs Hands-on Experience in constraint generation and management for hierarchical designs. Detailed Understanding of DFT Constraints. Hand-on Synthesis & STA Experience on LowerNode Technologies with Synopsys/Cadence Tools. Hands-on Experience on Equivalent Checks with Synopsys / Cadence Tools. Good knowledge of Timing Budgets. Knowledge of Perl / TCL / Python scripting language Experience in multi-voltage designs using CPF/UPF. Good understanding of the Chip Interface Constraint Generation & Timing Closure. Hands-on experience in power analysis using PTPX Good understanding of VHDL / Verilog Constructs. Responsibilities Responsible for Block/ Chip Tile Synthesis to achieve the best PPA. Constraint Generation & Maintenance for Block /SOC for sophisticated hierarchical Designs for all the Modes. Interaction with Design, DFT, IP& PD teams for Timing Convergence & Resolving Constraint Conflicts. Able to work on low-power & verify low-power intentwith minimal direction. Responsible for Logical equivalence checks & Low Power Checks. EarlyRTL analysis for Clocking, Power, DFT coverage & suggestions to the Designer on the improvements. Support Verification team to enable GLS. Contact: Uday Mulya Technologies



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