Senior ESD Engineer

2 weeks ago

Hyderabad, India GLOBALTALEX PRIVATE LIMITED Full time
Job Responsibilities

Conduct ESD/LUP research and experiments to investigate how to design-in the best ESD and latch-up design and layout solutions that minimize product defects due to electrostatic discharge (ESD) or latch-up (LUP) events.Design ESD test structures to fully evaluate the high current and voltage properties of the ESD IO, input or power clamps circuits.Assess the fundamental ESD properties of each type of ESD circuit elements, from active diffusions to BEOL metal layers, by wafer level transmission line pulse (TLP and vf-TLP) measurements to develop on-chip protection from ESD and or LUP events.Analyze ESD and latch-up (LUP) test structure data and generate ESD/LUP design rules and Guidelines.Develop and expand the ESD and latch-up circuit models based of the measured ESD data.Supervise and arrange full-chip ESD design review process (Schematic and Pathfinder analysis) for each design prior to tapeout.Apply Pathfinder type ESD current density and resistance verification tool to ensure full die layout meet all ESD design rule requirements.Lead and coordinate first silicon ESD and latch-up design validation tests and perform root cause ESD and LUP analysis, as vital, to ensure that product meets Micron's minimum qualification requirements.Continually improve product design and reliability by introducing innovative ESD designs.

Successful candidates for this position will have:A proven understanding of advanced semiconductor device physics, including deep submicron CMOS devices.A good understanding of groundbreaking CMOS process technology and electrical circuit analysis.Experience in Cadence design tools for design, layout, and verification tools.Hands-on experience in ESD characterization analysis using wafer level transmission line pulse (TLP) test equipment.Experience waveform generators, oscilloscopes, source/measure units, Agilent and/or Keithley parametric analyzers/testers, and impedance analyzers.Familiarity with ESD analysis tools like PERC or Path-Finder or similar software tools.Strong data analysis skills are required to extract the high current ESD properties and develop ESD/Latch-up design rules for critical ESD circuits.Strong oral and written communication skills are required to provide ESD/LUP technical leadership with diverse worldwide teams in Design, Product Engineering, R&D characterization, and Quality Assurance teams.Minimum Qualifications:A BS Electrical Engineering, Microelectronics, with 3-5 years of experience, ORA MS in Electrical Engineering, Microelectronics with 2 years of experience, ORA Ph.D. in Electrical Engineering, MicroelectronicsPreferred Qualifications:An MS/Ph.D. in Electrical Engineering, Microelectronics, or related field, with 8+ years of experience.

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