Ip/SOC Verification Engineer

2 days ago


New Delhi, India ACL Digital Full time

Senior Verification Engineer Email: WhatsApp: Location:Bangalore (Hybrid — 2 days/week onsite) Notice Period:Less than 30 days only Experience - 5 - 30 YearsJD 1 — Requirement: 1 Requirement Role: Senior Design Verification Engineer (15+ Years Experience) (Designation Based on the Final Discussion will decide with mutual understanding)Qualifications: BE / BTech / MTech in EE / EC / ECE Required Skills: 15+ years of hands-on Design Verification experience Strong expertise in verification of variousIPs and SoCs Excellent experience withVerilog Strong experience inSystemVerilog & UVM methodology Good understanding ofSoC verification ,C , and related verification flowsJD 2 — Requirement: 2 Req Role: Design Verification Engineer (8+ Years Experience) Qualifications: BE / BTech / MTech in EE / EC / ECE Required Skills: 8+ years of Design Verification experience Strong experience inIP Verification ,SystemVerilog , andUVM Excellent knowledge ofDV concepts and fundamentals Hands-on experience withVerilog Strong understanding ofSoC verification ,C , and SV/UVM methodologyJD 3 — Requirement: 4 Req Role: Design Verification Engineer (5+ Years Experience) Qualifications: BE / BTech / MTech in EE / EC / ECE Required Skills: 5+ years of Design Verification experience Experience inIP or SoC DV Strong understanding ofDV fundamentals Hands-on experience withVerilog Mandatory experience withSystemVerilog & UVM methodology



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