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Senior Design Verification Engineer
2 months ago
Job Description :
1. Must Have: GLS or SoC or IP Verification
2. Experience Languages: System Verilog
3. Methodologies: OVM/UVM/VMM
4. Protocols: PCIE/NVMe/DDR/Ethernet
5. Candidate must have expertise in System Verilog.
6. Experience in ARM base SoC Verification
7. Strong Analytical skills are desirable if having worked
8. Hands-on experience on Assertions and Functional Coverage
9. Automation of verification flow with Python/Perl in an industrial setting
10. Independent, self-motivated, team player and able to follow through
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