Senior Staff Engineer-DFT

2 weeks ago

india Mulya Technologies Full time

Senior Staff Engineer/ Staff DFT (5-10 years experience)

Location: Bangalore


Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.

Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?

Are you interested in developing novel and exclusive technology in a cutting-edge industry?

Are you looking to develop and refine your expertise working with a talented and diverse team spanning across key markets?

Would you like to make your mark by contributing to new applications that will transform and improve our daily lives?

If the answer is YES, then join the Apex Semiconductor team to embark on a journey towards enabling innovative chip design solutions. We have teams in Santa Clara, California and Bangalore, India. We are looking for dynamic applicants who are driven to make a difference in the technologies of tomorrow.

  • nt physical design tools preferably Cadence Innovus.



Senior Staff Design Engineer/Staff, DFT (5-10 years experience)

Location: Bangalore

The selected candidate will be a key contributor who is responsible for DFT logic design, implementation, verification and vector generation..



Responsibilities

  • Implementing DFT architecture features in the design.
  • SCAN insertion, scan DRC analysis and debug.
  • Achieving high SCAN coverage and low DPPM.
  • ATPG vector generation and ATE BringUp.
  • JTAG implementation and verification.
  • MBIST and JTAG implementation and verification.
  • IP-SOC integration methodology and Implementation of DFT structures to support IP test requirements.
  • Contributions to overall DFT flow / automation.
  • Contributions to SCAN, MBIST and JTAG timing constraints/analysis.
  • Simulation and Verification of DFT structures in the design

Requirements

  • BTech/MTech preferred.
  • Strong understanding of DFT methodologies and experience in standard DFT tools.
  • Experience on SoCs with multiple scan chains and clocks.
  • Hands On experience in SCAN/MBIST/JTAG implementation at chip & block level.
  • Knowledge on DFT simulations and debugging.
  • Knowledge on Test mode timing constraint development and analysis is a plus.
  • Understanding of test compression and ATE debug is a plus.
  • Having strong scripting abilities is a plus.




Contact:

Uday

Mulya Technologies

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