Principal Engineer, DEG Layout

2 weeks ago

hyderabad, India Spectrum Consultants India Private Limited Full time
Principal Engineer, DEG Layout Summary
Experience Required:
12 - 20 Years
Job Term:
Permanent
Location:
Hyderabad
Category:
Semiconductor Design
World leader in innovative memory solutions
Role and Responsibilities
Provide leadership in building and growing a Custom layout team from the ground up to support Micron’s global DRAM layout requirement;
Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design, enabling architecture analysis.
The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment.
Independent with strong analytical skills, creative thinking and self-motivated.
Provide leadership in developing Analog and custom layout to meet schedule and breakthrough;
Provide leadership in training the team’s technical skills and cultural healthiness.
Effectively communicating with Global engineering teams to assure the success of the layout project.
Organize, prioritize, and handle logistic on tasks and resource allocations for multiple projects.
Lead performance and development of team members.
Running hiring and retention.
As a critical member of the core DRAM leadership team in India, contribute to the overall success of the Micron DRAM India operation.
Qualification/Requirements
15 + year experience in analog/custom layout in advanced CMOS process.
Minimum 4+ years developing teams and project experience.
Should have experience in leading multiple project and Tape-out.
Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
Must have strong skills in layout and floor planning skills and manual routing.
Strong ability to build, and continuously develop a premier analog/mixed-signal layout team
Experienced in running multiple Custom IC layout projects
Excellent verbal and written communication skills required.
Capable of working in a multi-functional, multi-site team environment in multiple time zones.
Previous work experience in DRAM/NAND layout design is desirable however not mandatory.
Education
BE or MTech in Electronic/VLSI Engineering.

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