Lead Analog Mixed Signal Engineer – Expertise in Timing Closure

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to various Business Units/SoCs within AMD. The ideal candidate will get to work with Circuit and FE Architects on the design and implementation of complex high speed Analog Mixed Signal IPs with significant Digital and Analog content. KEY RESPONSIBLITIES: Architect the analog-digital interface timing boundary for high-speed analog mixed signal IP designs. Design high speed custom digital sub-modules for high-speed DDR PHY classes and die-to-die PHY. Use the performance-power-reliability trade off matrix to achieve IP goals. Define the appropriate margining methodology and scope for data, clock and async timing paths. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design and/or flow fixes. Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays in deep-nm tech nodes for various types of data interfaces and clock propagation schemes. Provide technical guidance to junior team members. Use scripting skills to meet efficiency and quality goals across all timing workflows. PREFERRED EXPERIENCE: 15+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Experience with SerDes or DDR PHY digital logic layer implementation is required. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop analysis. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Strong communication skills with ability to ability to comprehend and present ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess fundamentals and knowledge of analog mixed signal circuits, timing collaterals and constraints. Proficient in AMS design flows, tools and methodologies. Experience in evaluating and adopting new tools and methodologies to improve design processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Location- Bangalore/ Hyderabad #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.PMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to various Business Units/SoCs within AMD. The ideal candidate will get to work with Circuit and FE Architects on the design and implementation of complex high speed Analog Mixed Signal IPs with significant Digital and Analog content. KEY RESPONSIBLITIES: Architect the analog-digital interface timing boundary for high-speed analog mixed signal IP designs. Design high speed custom digital sub-modules for high-speed DDR PHY classes and die-to-die PHY. Use the performance-power-reliability trade off matrix to achieve IP goals. Define the appropriate margining methodology and scope for data, clock and async timing paths. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design and/or flow fixes. Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays in deep-nm tech nodes for various types of data interfaces and clock propagation schemes. Provide technical guidance to junior team members. Use scripting skills to meet efficiency and quality goals across all timing workflows. PREFERRED EXPERIENCE: 15+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Experience with SerDes or DDR PHY digital logic layer implementation is required. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop analysis. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Strong communication skills with ability to ability to comprehend and present ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess fundamentals and knowledge of analog mixed signal circuits, timing collaterals and constraints. Proficient in AMS design flows, tools and methodologies. Experience in evaluating and adopting new tools and methodologies to improve design processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Location- Bangalore/ Hyderabad #LI-PK2Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.