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Principal Engineer
3 months ago
Seeking an
ASIC Architect/micro-Architect
for Micron’s ASIC architecture team.Architect should have solid understanding and experience with RTL design (IP, SoC) DV (Coverage concepts) and implementation flow –(synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop) – and deep understanding of how architecture decisions impact these flows.Architect will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities for Micron’s leading edge ASIC storage controllers.Candidate should be highly motivated with strong communication skills, attention to detail, and quality oriented.Responsibilities include, but not limited to:Reviewing product, System and FW requirementsCollaborate with ASIC architects and system architects to define and document the feature sets and data/control flows implemented by the controller and each of its component IPs.Defining requirements for ASIC design, verification, and physical implementation teams.Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions.Reviewing and configuring 3rd party IPs.Supporting other teams in the ASIC organization and reviewing their workSupporting product teams with documentation, code-reviews, and silicon debugContinuously finding opportunities for improving design quality and design practicesMinimum Qualifications:10+ years of ASIC experienceRTL design experience in Verilog/System VerilogKnowledge and experience in various aspects of SOC design, verification, and implementation flowsExperience with low-power design techniquesScripting and Unix shell language experience: Perl, Python, Unix shell scriptsAbility to read and understand SW codeUnderstanding of CPU and memory architectures, data path pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologiesPreferred Skills:Knowledge of PCIe + CXL is an advantageDesign/Architecture experience with high-speed serial and parallel interfaces ( PCIe/UCIe, DDR, LPDDR)Design/Architecture experience with CHI, Coherency, Memory Controller, Fabric/NoCExperience with HW modeling languagesFamiliarity with Security and RAS design is an advantageEducation :, BS/BE (Electronics)
