RTL Engineer/ RTL Lead and above

2 days ago

Bengaluru, India Tessolve Full time
Opportunity With Tessolve Semiconductor- Bangalore
Hi All,
we are hiring RTL design engineer and design verification engineer for Bangalore location.
Exp: 5+ yr exp
Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass
We are hiring for RTL ASIC engineer
7f work experience in ASIC/IP Design.
Experience in Logic design / RTL design
Experience is IP design and integration.
Experience in using the tools in ASIC development such as Lint and CDC are a must.
Experience in Synthesis / Understanding of timing concepts is a plus.
Good to have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
Design verification engineer :
Exp: 5 to 20 yrs
Location : PAN INDIA
• IP verification Using SV/UVM
• SOC Verification using C/SV
• Third Party VIP Integration
• Interconnect Protocols: AHB, AXI, APB
• SOC Interfaces: GPIO, SPI, I2C, UART (3+)
• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
• Memory Interfaces: DDR or HBM I/O (10+)
• Coverage Closure: Code, Functional and Toggle • Tools: Synopsys VCS or Cadence Incsive • Technical Documentation: Testbench Specification, Test Plan Specification • Foundry Porting Experience: Technology Library Conversion Related Changes Verification
Interested candidates, Kindly share updated cv to or connect on
Regards, Gayatri Kushe )

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