Senior Physical Design Engineer

3 weeks ago


bangalore, India Mulya Technologies Full time

Senior Physical Design Engineer

Client: Top10 Semiconductor Organization in the world

Location: Bangalore

Senior Engineer - ASIC Physical Design


Responsibilities


  • Subsystem Place and Route, Physical verification, Timing closure.
  • Resolve congestion, timing, power, runtime related issues in Physical design
  • Experiment and execute techniques to improve PPAS.
  • Coordination with chip level build activities, fully resolves schedule dependencies from his/her ownership
  • Understand dependencies of his/her deliveries in chip level scope, and highlight gating issues on time, every time; deliver on time to void dependencies

Requirements


  • A minimum of 5+ years of exclusive partition physical design experience
  • Fully aware of atleast one EDA tool to do Place and Route.
  • Is very good with at least one programming language like TCL/PERL
  • Works on ambitious, results-oriented schedule
  • Excellent at debug, a quick learner & has applied analytical skills on job
  • Bachelors of Engineering/Master of Technology in E&C/Electrical/Computer Science.

Preferred Skills


  • Strong verbal communication skills
  • Analog/MS/RF layout/design experience
  • Multi-mode constraint design experience
  • Low power checks, Formal verification experience
  • ESD - Need, Implement, Check mechanism - exposure to
  • Power integrity/Signal integrity experience



Contact:

Uday

Mulya technologies

Email :



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