Senior Principal Engineer

3 weeks ago

Delhi, India Mulya Technologies Full time
Senior Principal Engineer/ Principal Engineer, Physical Design (10-20 years experience)Location: Bangalore

Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?Are you interested in developing novel and exclusive technology in a cutting-edge industry?Are you looking to develop and refine your expertise working with a talented and diverse team spanning across key markets?Would you like to make your mark by contributing to new applications that will transform and improve our daily lives?If the answer is YES, then join the Apex Semiconductor team to embark on a journey towards enabling innovative chip design solutions. We have teams in Santa Clara, California and Bangalore, India. We are looking for dynamic applicants who are driven to make a difference in the technologies of tomorrow.

Senior Staff/Principal Engineer, PD (10-20+ years experience)Location: BangaloreYou will work with an elite team of physical design implementation engineers and have personal design responsibility, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.Less

ResponsibilitiesWork at various levels of implementation of hierarchical chip (Blocks and Top)Floor plan and partition, power plan, bump planIntegration of different sub-blocks and custom macros/IPsPhysical implementation of blocksBlocks and top-level timing IR analysis and closurePhysical VerificationDevelop, support and maintain physical design flows and methodologiesRequirementsB.Tech / M.Tech from a reputed university with 10-20+ years of experience.Good knowledge of VLSI process and device characteristics.Experience doing physical design targeted to the 5nm/7nm/16nm FinFet process.Good knowledge of cell libraries various views and models.Good understanding of static timing analysis (STA), EM/IR and sign-off.Strong hands-on experience with: Chip Level / Sub-chip level floor planning, partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification – block and chip level.EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC etc.Good software and scripting skills (Python, tcl).Good communication skills and the ability and desire to work as part of a team.Self-driven individual and an excellent team player.Good communication abilities.

Contact:UdayMulya "Mining The Knowledge Community"

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