Senior Staff Engineer, and Digital Verification Manager

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Job SummaryThis position is for a Senior Staff Engineer, and Digital Verification Manager. The primary responsibilities include, but will not be limited to, managing in a hands-on fashion to technically guide test plan development, defining the verification methodology and infrastructure, tracking deliverables to ensure timely execution with high quality.

As a technical leader/manager, this person is also responsible for leading/hiring engineers and building a strong design verification team.

The individual will work closely with the digital design, verification, and Product Development teams in India Design Center and other design centers. This position is located in our India Design Center (IDC) in Chennai, India.

Roles & ResponsibilitiesThis position has responsibility for:Development and deployment of verification and validation environment of digital circuits from scratch and (or) adapt and improve upon existing environmentDesign, build, and maintain verification test suites to fully verify ICsDeliver detailed test plans for verification of complex digital design blocksDefinition of verification simulation tool flowIdentify and write all types of coverage measures for stimulus and corner-casesDebug tests with design engineers to deliver functionally correct design blocks.Close coverage measures to identify verification holesWork with interdisciplinary teams to identify automation and tool requirementsManage Verification Team: Manage a team of verification engineers. Lead and maintain an efficient and technically proficient staff required to complete product development goals, manages team resources and schedules, and manages career development of team members, set staff’s goals and conduct performance reviews, recruit and select candidates, provide orientation and trainingMentor verification engineers as neededSupport independent product development and provide support for other design groupsMaintain a positive growth culture in IDC

Competency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies:Displaying Technical Expertise:

Keeps his/her technical skills current; effectively applies specialized knowledge and skills to perform work tasks; understands and masters the technical skills, knowledge, and tasks associated with his/her job; shares technical expertise with othersDriving for Results:

Aggressively pursues challenging goals and objectives; will to put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward workMaking Accurate Judgments and Decisions : Bases decisions on a systematic review of relevant facts and information; avoids making assumptions or rushing to judgment; provides clear rationale for decisionsWorking with Ambiguity : Achieves forward progress in the face of inadequately defined situations and/or unclear goals; able to work effectively with limited or partial informationCritical Thinking : Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situations

Minimum Qualifications (Experience and Skills)Typically requires 12+ years of experience in digital design verification, depending on education level6 years of demonstrated technical leadership2 years’ experience in leading or managing individuals and teamsProficiency in logic design verificationFamiliar with Assertion based verificationFamiliar with Code and functional coverage metricsAbility to debug and perform root cause failure analysis at RTL levelExperience in industry standard verification tools and methodologies using SystemVerilog, UVMSoftware programming ability in high level language – C, C++, Perl, PythonFamiliarity with interface specifications such as MIPI, SPI or I2CFamiliarity with Cadence and Synopsys tool suitesFamiliarity with interface specifications such as MIPI, SPI or I2CFamiliarity with DFT and scan insertion

Preferred QualificationsDevelopment and implementation of efficient verification strategies in diverse environments, from 20K gate digital blocks inside mixed signal chips with short development cycles to 1M+ gate SOCs which may include embedded processorsKnowledge of Mixed-Signal design and behavioral modeling of analog/mixed-signal/RF blocksUse of FPGA to validate digital RTL and gates is a plusDesign verification in a mixed-signal or RF ASIC

Education RequirementsMasters/Bachelors’ Degree in Electronics Engineering

Work EnvironmentThis job operates in a professional office environment. This role routinely uses standard office equipment.

Physical DemandsThe physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.

pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents:

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