Sr. Asic Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. Key Responsibilities Complex IP designs including control and datapath. Understand the functional and performance requirements of the IOHUB within various SOCs Signoff IP quality for delivery into SOC Effectively communicate with multi-disciplined teams located across the globe Preferred Experience Candidate's Experience - 6+ years Proven RTL design experience on large ASIC development projects Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc) Strong background in Verilog and System Verilog Strong analytical skills and attention to detail Excellent written and communication skills Understanding of the IP integration and interactions within an SOC Must be a self-starter and able to independently drive tasks to completion Demonstrates the ability to debug issues and quickly identify viable solutions Team player with proven leadership skills ACADEMIC CREDENTIALS: Bachelor's Degree in Computer Science or Computer Engineering or other relevant field Master's Degree preferred #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.THE ROLE: The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. Key Responsibilities Complex IP designs including control and datapath. Understand the functional and performance requirements of the IOHUB within various SOCs Signoff IP quality for delivery into SOC Effectively communicate with multi-disciplined teams located across the globe Preferred Experience Candidate's Experience - 6+ years Proven RTL design experience on large ASIC development projects Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc) Strong background in Verilog and System Verilog Strong analytical skills and attention to detail Excellent written and communication skills Understanding of the IP integration and interactions within an SOC Must be a self-starter and able to independently drive tasks to completion Demonstrates the ability to debug issues and quickly identify viable solutions Team player with proven leadership skills ACADEMIC CREDENTIALS: Bachelor's Degree in Computer Science or Computer Engineering or other relevant field Master's Degree preferred #LI-PM2Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.