AMS Verification Engineer

5 days ago

Bengaluru, India ACL Digital Full time

We are looking for a motivated candidate to work with our Design Verification team. The role involves working on real number modeling and verification of mixed-signal designs using System Verilog and UVM methodologies. This is a hands-on opportunity to gain experience in advanced verification flows and contribute to real-world projects.Exp: 3+ YearsLocation: BangaloreNotice period: Immediate to 30 daysKey Responsibilities:Develop and validate real number models (WREAL) for analog/mixed-signal blocks.Integrate real number models into digital verification environments.Write and maintain SystemVerilog/UVM testbenches.Perform functional and regression testing of mixed-signal IPs.Collaborate with design and verification engineers to debug and resolve issues.Document modeling and verification strategies and results.Required Skills:Good coding skill in Verilog(VAMS) / SV real number models.Strong understanding of digital and analog design concepts.Familiarity with SystemVerilog and UVM methodology.Exposure to real number modeling (wreal, AMS modeling concepts).Basic scripting skills (Python, Perl, or Shell).Good problem-solving and communication skills.Project experience in mixed-signal design or verification.Knowledge of simulation tools like Cadence/Xcelium, Synopsys VCS, or Mentor Questa.

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