
DV Engineer(GLS)
3 weeks ago
Location: BangaloreExperience: 5 to 7yrsJob Description:Total experience (5 -7 years) with SOC GLS experience of minimum 3+ yearsHands on experience in GLS (Zero Delay, SDF, PAGLS)Excellent debugging skills and fixing issuesKnowledge in SV/UVM and test bench flowGood experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.Understanding of SOC Architecture
-
DV Engineer
2 weeks ago
Bengaluru, Karnataka, India, Karnataka Modernize Chip Solutions Full timeRole:Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV-IP with Ethernet/PCIENP: Immediate to 30 daysLoc: HYDExp: 10+ yrsRole:Design Verification EngineerSkill: DV with Soc, GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with...
-
Dv engineer
2 weeks ago
Bengaluru, India Modernize Chip Solutions Full timeRole: Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV-IP with Ethernet/PCIENP: Immediate to 30 daysLoc: HYDExp: 10+ yrsRole: Design Verification EngineerSkill: DV with Soc, GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with...
-
DV Engineer
2 weeks ago
Bengaluru, Karnataka, India, Karnataka Modernize Chip Solutions Full timeRole:Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with Soc, Arm ProcessorNP: Immediate to 30 daysLoc: BLRExp: 6+ yrs
-
Dv engineer
1 week ago
Bengaluru, India Modernize Chip Solutions Full timeRole: Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with Soc, Arm ProcessorNP: Immediate to 30 daysLoc: BLRExp: 6+ yrs
-
Dv engineer
6 days ago
Bengaluru, India Modernize Chip Solutions Full timeRole: Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with Soc, Arm ProcessorNP: Immediate to 30 daysLoc: BLRExp: 6+ yrs
-
SoC DV CPU
2 weeks ago
Bengaluru, Karnataka, India Quest Global Full time ₹ 20,00,000 - ₹ 25,00,000 per yearJob Requirements Job DescriptionResponsibilities:Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:Active involvement with architecture team during the spec definition phaseVerification strategy definition along with Verification plan...
-
DV Engineer(GLS)
2 weeks ago
Bengaluru, India Capgemini Engineering Full timeLocation: Bangalore Experience: 5 to 7yrsJob Description:Total experience (5 -7 years) with SOC GLS experience of minimum 3+ yearsHands on experience in GLS (Zero Delay, SDF, PAGLS)Excellent debugging skills and fixing issuesKnowledge in SV/UVM and test bench flowGood experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.Understanding of SOC...
-
DV Engineer(GLS)
4 days ago
Bengaluru, India Capgemini Engineering Full timeLocation: Bangalore Experience: 5 to 7yrsJob Description:Total experience (5 -7 years) with SOC GLS experience of minimum 3+ yearsHands on experience in GLS (Zero Delay, SDF, PAGLS)Excellent debugging skills and fixing issuesKnowledge in SV/UVM and test bench flowGood experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.Understanding of SOC...
-
DV Engineer(GLS)
4 days ago
Bengaluru, India Capgemini Engineering Full timeLocation: BangaloreExperience: 5 to 7yrsJob Description:- Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years- Hands on experience in GLS (Zero Delay, SDF, PAGLS)- Excellent debugging skills and fixing issues- Knowledge in SV/UVM and test bench flow- Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.- Understanding of...
-
DV Engineer(GLS)
4 weeks ago
Bengaluru, India Capgemini Engineering Full timeLocation: BangaloreExperience: 5 to 7yrsJob Description:- Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years- Hands on experience in GLS (Zero Delay, SDF, PAGLS)- Excellent debugging skills and fixing issues- Knowledge in SV/UVM and test bench flow- Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.- Understanding of...