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ASIC Front-End Design Engineer
4 weeks ago
Client - CONFIDENTIAL
NP - max 2 weeks
Location - South Korea (onsite role)
Candidates location - Preferred is India, Turkey,etc.
Job Title: ASIC Front-End Design Engineer (Senior Engineer and Principle Engineer)
Our company designs ASIC Accelerator Chips based on Samsung Foundry's 4nm FinFET process.
Recruitment division
- Front-End Engineer
Field
- RTL Design
- Chip Architecture
- Logic Verification
- FPGA Validation
Experience:
For Senior Engineer role- 2 to 8 years
For Principle Engineer role- 8+ Years
Education - Bachelor's degree or higher
Major
- electronics and semiconductor-related departments
For Senior Engineer Role:
Experience Requirements-
- Front-End Design Experience
- RTL Design, Verdi, VCS, Verilog
- FPGA Synthesis & Debugging
Preferences-
- STA(PrimeTime), HPC Design, AI Chip Design
For Principle Engineer Role:
Experience Requirements-
- Front-End Design Experience
- RTL Design, Verdi, VCS, Verilog, DC, PrimeTime (STA, PTPX)
Preferences-
- HPC Design, AI Chip Design
Welfare benefits:
round-trip airfare support
Support your initial two-week home until you find one
Regarding S-level human resources, it is possible to discuss the provision of lodging
incentives
Lunch meal support
severance pay
2 major insurances
annual leave
health checkups
medical expenses (within 700,000 won per year)
flexible work hours
children's tuition
childcare expenses for infants and toddlers, etc.
Submission documents and selection process Submission documents
- resume (+ career description) Selection process: document screening
1) Online Test (System SW/RTL, architecture)
2) Zoom meeting test 45-60 minutes and Zoom
Don't forget to attach updated resume.
Interested one can DM or email at-
Regards
Lucky Vashisth
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