Sr. Design Manager DFT

1 month ago

bangalore, India L&T Semiconductor Technologies Full time

Role - Sr. Design Manager - DFT

Stream - R&D

Reporting To - Chief Development Officer / Global Head of Engineering

Location -Bengaluru


COMPANY DESCRIPTION:


L&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company - a fabless company for designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.


Harnessing the engineering mastery of L&T, LTSCT is forging a path to a world-class semiconductor ecosystem rooted in India. We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.


We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.


JOB DESCRIPTION:


LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry leading solutions covering very cost sensitive, low power devices to highly integrated, high performance, multidomain devices compliant with the latest automotive and industrial safety and security standards.


AREAS OF RESPONSIBILITY:


The successful candidate will be expected to

  • Be the focal point and drive the global teams on advance technology node physical implementation and sign-off domains.
  • Continuously improve the process, methods and tools, driving the SOC chip development for lowest possible AUC (average unit cost) and highest yield quality
  • Drive chip implementation and sign-off activities.
  • Ensure Chip KPIs on Power, Performance, Area, Thermal & Schedule commitments are met predictably and consistently.
  • Work closely with Design Enablement, SOC architecture/design, Package, Post-Silicon test teams and Foundry partners to meet the NPI and technology entitlement.
  • Need to work with peers across the business to drive change across L&T Semiconductor Technologies (LTSCT) to have common methods that work across the whole organization in partnership and collaboration with stakeholders and influence the direction taken.



Qualifications:


  • Can – do attitude; openness to new environment, people and culture
  • Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science
  • At least 15 years of experience in related domains and have working knowledge of industry standard digital EDA toolkits.
  • Must be conversant on EDA tools such as Cadence iSpatial, Fusion Compiler, Redhawk, Primetime, Tempus, Conformal/Formality etc
  • Have expert level knowledge on E2E physical implementation flows such as Synthesis, Floorplan, Placement, CTS, Route/ECOs using industry standard tools.
  • Candidate must be proficient with STA, PDN, PDV, Logic ECOs and Chip Sign-off
  • Must be proficient on low power implementation techniques.
  • Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus.
  • Strong drive & ability to coordinate work across a cross functional, highly experienced global team.

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