Design Verification Engineer
4 weeks ago
Roles And Responsibilities :
As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.
Required Technical And Professional Expertise :
- Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
- Understanding of verification tools like Simulator, Synthesis etc.
- Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
- Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
- Excellent written and verbal interpersonal skills
- Self-motivated and great teammate
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Mirafra Technologies
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Bangalore/Anywhere in India/Multiple Locations, IN Mirafra Tehchnologies Full timeProficiency in Verilog and SystemVerilog for hardware description and verification.Methodologies : - Experience with Universal Verification Methodology (UVM) is preferred, with familiarity in OVM and VMM.Scripting :- Knowledge of scripting languages such as Perl and C-shell for test automation and verification environment setup.Additional Skills :-...
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Mirafra Technologies
2 weeks ago
Bangalore/Anywhere in India/Multiple Locations Mirafra Tehchnologies Full timeProficiency in Verilog and SystemVerilog for hardware description and verification.Methodologies : - Experience with Universal Verification Methodology (UVM) is preferred, with familiarity in OVM and VMM.Scripting :- Knowledge of scripting languages such as Perl and C-shell for test automation and verification environment setup.Additional Skills :-...
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