STA Engineer

Principal Engineer STA (10-15) years experience)Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?Are you interested in developing novel and exclusive technology in a...

Senior Principal Engineer/ Principal Engineer, STA (10-20 years experience)Location: BangaloreJoin Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?Are you interested in...

Senior Principal Engineer/ Principal Engineer, STA (10-20 years experience)Location: BangaloreJoin Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?Are you interested in...

Senior Principal Engineer/ Principal Engineer, STA (10-20 years experience)Location: BangaloreJoin Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?Are you interested in...

Skill required - STA (Static Timing Analysis) & Constraints Handling.Exp: 3 to 15 Yrs.JOB DESCRIPTION:We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast-paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm...

Design For Test(DFT)DFT Skill set required with below split of 10 DFT CW - preferably with 5-7 yrs of exp.* 2 CW : Experience with MBIST/Mint flows and methodology* 3 CW : Experience with SSN architecture/implementation/validation* 4 CW : Experience with Taplinks/STF/BSCAN implementation/validation* 1 CW : Experience with Intel...

1. Design For Test(DFT)DFT Skill set required with below split of 10 DFT CW - preferably with 5-7 yrs of exp.* 2 CW : Experience with MBIST/Mint flows and methodology* 3 CW : Experience with SSN architecture/implementation/validation* 4 CW : Experience with Taplinks/STF/BSCAN implementation/validation* 1 CW : Experience with Intel...

Job DescriptionJob title: Lead STA EngineerExperience: 7-10 yearsPrimary Responsibilities:The STA and Methodology Engineer is expected to work closely with the Foundation IP teams (Standard cell, IO, and Memories teams) and NXP NPI design teams spread across various BL's to support timing and Power analysis and closure while making sure a seamless use of...

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you...

Below are the open positions!!!STA : 4+ Years Experience in chiptop / Top Level / Block level / Fullchip /#Tweaker #Tempus#Primetime#PDN/ #IR_Drop/ #EMIR : 3+ Yrs > Voltas, Redhawk_SC, EMIR, Power integrity Physical Design: 4+ YrsExperience in Block level / Full chip /Top Level#Innovus #ICC2Synthesis: 3+ Yrs.Experience in Core Synthesis#Genus #Fusion...

ASIC Front-End Design Engineer Recruitment Notice (Principle Engineer)Recruitment division Front-End EngineerField Front-End Design (Implementation, DC, STA) RTL Design Chip Architecture Logic VerificationClient South Korea Onsite opportunity Experience : Title: ASIC frontend deisgn engineerYoE 2+ yearsTitle : ASIC fronteend design Principal engineerYoE 8+...

Location: Bangalore/HyderabadExperience: 5-12yrsNotice Period: Immediate to 15 DaysPrimary Skills : Physical Design, CTS, STA & Physical Verification· Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.· Should have experience on Physical Design Methodologies...

We are looking for Multiple roles to fullfill San Diego, CA and Austin, TX (two different positions)To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM. Work On PD projects.Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure...

Wipro HiringPhysical Design Engineers / LeadsExperience : Min 5-18 Years.In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.· Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology...

Quest Gobal is looking to hire for expertise physical design engineer, experience with Innovus tools,PNR.Location:: Bangalore,IndiaJob Description ::5+ years industry experience requiredExperience with Hierarchical design is a plusExperience with ICC2 or InnovusExperience in taping out multiple technologies is a plusExpertise in floorplanning large blocks or...

Client: HyperhireRole: ASIC Front-End Design Engineer (Fulltime Permanent Role)Experience: 2+ yearsWorkplace : onsiteBudget : OpenClient Location : Seoul , South KoreaNotice period : 2 WeekField:Front-End Design (Implementation, DC, STA)- RTL Design- Chip Architecture- Logic VerificationMajor:- electronics and semiconductor-related departmentsExperience...

Client: HyperhireRole: ASIC Front-End Design Engineer (Fulltime Permanent Role)Experience: 2+ yearsWorkplace : onsiteBudget : OpenClient Location : Seoul , South KoreaNotice period : 2 WeekField:Front-End Design (Implementation, DC, STA)- RTL Design- Chip Architecture- Logic VerificationMajor:- electronics and semiconductor-related departmentsExperience...

We are looking for Multiple roles to fullfillSan Diego, CA and Austin, TX (two different positions)Todo Floor planning, P&R, timing closure SI prevention/fixing, powerplanning, CTS, PV and I/R drop for Block as well as Top level MSM.Work On PD projects.Ableto deal with MSM Top level complexity from FP, Placement, CTS, Routingand timing closure Must be able...

Mirafra Technologies Hiring Physical Design Engineers Innovus Expert Engineers:Experience 4 15 yearsNotice Period 0 to 90 daysPlease find the Job Description Below:Must hands on experience with a solid complex (SOC/sub-systems/SWRPs) implementation and strong understanding in PG/floorplan and physical design flows and methodologies, place and route using...

Mirafra Technologies Hiring Physical Design Engineers Innovus Expert Engineers:Experience 4 15 yearsNotice Period 0 to 90 daysPlease find the Job Description Below:Must hands on experience with a solid complex (SOC/sub-systems/SWRPs) implementation and strong understanding in PG/floorplan and physical design flows and methodologies, place and route using...