Lead Physical Design Engineer

5 days ago

Bengaluru, India ACL Digital Full time

Job Title: Lead Physical Design EngineerExperience: 7+ YearsLocation: Bangalore/HyderabadEmployment Type: Full-timeIndustry: Semiconductors / ASIC / VLSI / SoC DesignJob Summary:We are seeking a highly experienced and technically strong Lead Physical Design Engineer to drive RTL-to-GDSII implementation for complex SoC or block-level designs. The ideal candidate will lead a team of engineers, oversee physical design execution, and ensure successful signoff and tapeout across advanced process nodes.Key Responsibilities:Own and drive block/full-chip physical implementation from RTL to GDSII.Lead floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.Guide timing closure, power integrity (IR/EM), DRC/LVS, antenna, and reliability checks.Define and execute physical design strategies to meet aggressive PPA targets.Interface with cross-functional teams including RTL, STA, DFT, power, and package teams.Plan and manage physical design activities for successful project delivery.Implement low-power design techniques (multi-VDD, power gating) using UPF/CPF.Drive physical design reviews, methodology development, and flow improvements.Mentor and guide junior PD engineers; provide technical leadership and training.Required Skills and Experience:B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI.7+ years of strong experience in physical design implementation.Hands-on experience with industry tools:P&R: Synopsys ICC2, Cadence Innovus, Siemens NitroTiming: Synopsys PrimeTimeVerification: Calibre DRC/LVS, RedHawk, Tempus, VoltusStrong command over timing analysis, congestion management, ECOs, and layout optimization.Deep understanding of FinFET/advanced node design challenges (7nm/5nm/3nm).Scripting skills (Tcl, Perl, Python) for design automation and tool integration.Experience in tapeout and signoff processes with foundries like TSMC/Samsung/GF.Preferred Qualifications:Experience with hierarchical design and chip-level integration.Exposure to 2.5D/3D ICs, chiplets, HBM, or advanced packaging technologies.Knowledge of DFT insertion and formal verification tools.Familiarity with EDA tool flows customization and methodology development.Interested can share Cv to

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