Analog Layout Engineer

2 weeks ago

Bengaluru, India SILCOSYS Solutions Pvt. Ltd. Full time

Company Description

SILCOSYS Solutions collaborates with clients in developing flagship product lines such as mobile devices, complex routers/switches, consumer goods, storage solutions, and microprocessors. The company pioneers cutting-edge technologies that are pivotal and rare in the industry. Distinguished for crafting intricate SoCs, Silcosys Solutions is further known for its robust analog/mixed signal and software design teams.

Role Description

This is a full-time, on-site role for an Analog Layout Engineer located in Bengaluru. The Analog Layout Engineer will be responsible for designing layout for various analog circuits, ensuring adherence to circuit design specifications, and conducting physical verification. The role includes collaborating with the design team to optimize performance and reliability of the integrated circuits.

Role
: Layout Manager

Location
: Bangalore

Notice:
Immediate Joiner

Responsibilities:

  • Own custom layout for analog/mixed-signal blocks, including device placement, routing, guard rings, shielding, and symmetry for matching and noise isolation.
  • Execute physical verification and sign-off: DRC, LVS, ERC, and parasitic extraction; drive fixes and enable accurate post-layout simulations with the design team.
  • Plan floorplans, power routing, and critical signal paths; minimize parasitics and IR/EM risks; prepare clean GDS for tapeout.
  • Collaborate across design, CAD, and foundry teams to meet performance, schedule, and quality targets for AMS IP delivery in an SoC flow.

Qualifications:

  • 8–15 years in analog IC layout with proven tapeouts in CMOS/BiCMOS; strong grasp of matching, isolation, ESD structures, and reliability-aware layout.
  • Proficiency with Cadence Virtuoso and sign-off flows (Calibre/Assura/Pegasus) for DRC/LVS/PEX; confident in post-layout correlation practices.
  • Experience across block- to top-level integration and verification; comfort with deep-submicron design constraints and foundry rule compliance.
  • Effective communicator and collaborator with circuit designers on constraints, floorplans, and performance closure under schedule pressure.

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