Asic rtl engineer
3 weeks ago
Requirement Name : ASIC RTL / So C RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols) Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20 Location : Kochi, Bengaluru, Hyderabad, Pune, Noida Expertise in So C subsystem/IP design Expertise in IP design, Subsystem/Cluster and So C level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols - PCIe -DDR -Ethernet - I2 C, UART, SPI Expertise in setting up and using tools like -Spyglass Lint/CDC -Synopsys DC -Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews About Us: Wipro Limited (NYSE: WIT, BSE: , NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With nearly 245,000 employees and business partners across 65 countries, we deliver on the promise of helping our clients, colleagues, and communities thrive in an ever-changing world. Wipro is an Equal Employment Opportunity employer and makes all employment and employment-related decisions without regard to a person's race, sex, national origin, ancestry, disability, sexual orientation, or any other status protected by applicable law.
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Asic rtl engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / So C RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols)Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20Location : Kochi, Bengaluru, Hyderabad, Pune, NoidaExpertise in So C subsystem/IP designExpertise in IP design, Subsystem/Cluster and So C level integration...
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ASIC RTL Engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols) Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20 Location : Kochi, Bengaluru, Hyderabad, Pune, Noida Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level...
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ASIC RTL Engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols) Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20 Location : Kochi, Bengaluru, Hyderabad, Pune, Noida Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level...
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ASIC RTL Engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols)Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20Location : Kochi, Bengaluru, Hyderabad, Pune, NoidaExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using...
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ASIC RTL Engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols) Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20 Location : Kochi, Bengaluru, Hyderabad, Pune, Noida Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC...
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ASIC RTL Engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols)Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20Location : Kochi, Bengaluru, Hyderabad, Pune, NoidaExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using...
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ASIC RTL Engineer
4 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols)Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20Location : Kochi, Bengaluru, Hyderabad, Pune, NoidaExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using...
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ASIC RTL Engineer
3 weeks ago
Kochi, India Wipro Full timeRequirement Name : ASIC RTL / SoC RTL IP Design (IP RTL design targeted for SOC, Static checks, some basic protocols) Role : Senior Engineer / Technical Lead / Architect / Senior Architect Exp - 4 - 20 Location : Kochi, Bengaluru, Hyderabad, Pune, Noida Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level...
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Asic Rtl Design Engineer
2 weeks ago
Bengaluru, Hyderabad, Kochi, Pune, India Eminence Technosystem Full time ₹ 9,00,000 - ₹ 12,00,000 per yearExpertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC)PCIe/DDR/Ethernet - Any OneI2C,UART/SPI
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Senior RTL Design Engineer-Barcelona
1 week ago
Kochi, India Geesesquads Full timeRTL Engineers Description We have multiple open positions in our RTL team and we're looking for individuals with either a strong RTL or a strong architecture/microarchitecture background interested in working in several areas of a RISC-V design for an advanced technology node. In particular, areas of focus will be the processor pipeline, d-cache, i-cache,...
